參數(shù)資料
型號: M36WT864T70ZA6T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product
中文描述: 64兆位4Mb的x16插槽,多銀行,突發(fā)閃存和8兆位的SRAM為512k x16,內(nèi)存產(chǎn)品多
文件頁數(shù): 61/92頁
文件大?。?/td> 624K
代理商: M36WT864T70ZA6T
61/92
M36WT864TF, M36WT864BF
Figure 25. SRAM Low V
DD
Data Retention AC Waveforms, E1S Controlled
Figure 26. SRAM Low V
DD
Data Retention AC Waveforms, E2S Controlled
Table 28. SRAM Low V
DD
Data Retention Characteristics
Symbol
Parameter
Note: 1. All other Inputs at V
IH
V
DDS
–0.2V or V
IL
0.2V.
2. Tested initially and after any design or process that may affect these parameters.
t
AVAV
is Read cycle time.
3. No input may exceed V
DDS
+0.2V.
Test Condition
Min
Typ
Max
Unit
I
DDDR(1)
Supply Current (Data Retention)
V
DD
= 1.5V, E1S
V
DDS
–0.2V or
E2S
0.2V or
UBS = LBS
V
DDS
–0.2V, f = 0
5
10
μA
t
CDR(1,2)
Chip Deselected to Data
Retention Time
0
ns
t
R(2)
Operation Recovery Time
t
AVAV
ns
V
DR(1)
Supply Voltage (Data Retention)
E1S
V
DDS
–0.2V or E2S
0.2V or
UBS = LBS
V
DDS
–0.2V, f = 0
1.5
V
AI06287
DATA RETENTION MODE
tR
3.3V
tCDR
VDDS 2.7V
VDR> 1.5V
E1S or UBS/LBS
E1S
VDR– 0.2V or UBS = LBS
VDR– 0.2V
AI06288
DATA RETENTION MODE
tR
3.3V
tCDR
VDDS 2.7V
VDR> 1.5V
E2S
E2S
0.2V
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