參數(shù)資料
型號(hào): M34501M4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù): 76/113頁(yè)
文件大?。?/td> 1252K
代理商: M34501M4
Skip condition
Number of
cycles
Number of
words
Instruction
code
D
9
D
0
76
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D
9
D
0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D
9
D
0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D
9
D
0
Flag CY
2
16
TAB2
(Transfer data to Accumulator and register B from timer 2)
1
0
0
1
1
1
0
0
0
1
2
7
1
1
1
Grouping:
Description:
Timer operation
Transfers the high-order 4 bits (T2
7
–T2
4
) of
timer 2 to register B.
Transfers the low-order 4 bits (T2
3
–T2
0
) of
timer 2 to register A.
Operation:
(B)
(T2
7
–T2
4
)
(A)
(T2
3
–T2
0
)
TABAD
(Transfer data to Accumulator and register B from register AD)
1
0
0
1
1
1
1
0
0
1
2
7
9
1
1
Grouping:
Description:
A-D conversion operation
In the A-D conversion mode (Q1
3
= 0), trans-
fers the high-order 4 bits (AD
9
–AD
6
) of
register AD to register B, and the middle-order
4 bits (AD
5
–AD
2
) of register AD to register A.
In the comparator mode (Q1
3
= 1), transfers
the middle-order 4 bits (AD
7
–AD
4
) of register
AD to register B, and the low-order 4 bits
(AD
3
–AD
0
) of register AD to register A.
Operation:
In A-D conversion mode (Q1
3
= 0),
(B)
(AD
9
–AD
6
)
(A)
(AD
5
–AD
2
)
In comparator mode (Q1
3
= 1),
(B)
(AD
7
–AD
4
)
(A)
(AD
3
–AD
0
)
(Q1
3
: bit 3 of A-D control register Q1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABE
(Transfer data to Accumulator and register B from register E)
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
Grouping:
Description:
Register to register transfer
Transfers the high-order 4 bits (E
7
–E
4
) of
register E to register B, and low-order 4 bits
of register E to register A.
Operation:
(B)
(E
7
–E
4
)
(A)
(E
3
–E
0
)
TABP p
(Transfer data to Accumulator and register B from Program memory in page p)
0
0
1
0
0
p
4
p
3
p
2
p
1
p
0
0
p
1
3
Grouping:
Description:
Arithmetic operation
Transfers bits 7 to 4 to register B and bits 3 to
0 to register A. These bits 7 to 0 are the ROM
pattern in ad-dress (DR
2
DR
1
DR
0
A
3
A
2
A
1
A
0
)
2
specified by registers A and D in page p.
p is 0 to 15 for M34501M2, and p is 0 to 31
for M34501M4/E4.
When this instruction is executed, be careful
not to over the stack because 1 stage of
stack register is used.
Note:
Operation:
(SP)
(SP) + 1
(SK(SP))
(PC)
(PC
H
)
p
(PC
L
)
(DR
2
–DR
0
, A
3
–A
0
)
(B)
(ROM(PC))
7–4
(A)
(ROM(PC))
3–0
(PC)
(SK(SP))
(SP)
(SP) – 1
8
+p
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