參數(shù)資料
型號: M34501M4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 52/113頁
文件大小: 1252K
代理商: M34501M4
52
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
0
1
0
1
0
1
0
1
W2
1
0
0
1
1
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
Prescaler control bit
Prescaler dividing ratio selection bit
Timer 1 control bit
Timer 1 count start synchronous circuit
control bit
Stop (state retained)
Operating
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count source
Timer 1 underflow signal
Prescaler output (ORCLK)
CNTR input
System clock
Timer 2 control bit
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 2 count source selection bits
0
1
0
1
W2
0
0
1
0
1
W1
3
W1
2
W1
1
W1
0
Timer control register W1
R/W
at RAM back-up : 0000
2
at reset : 0000
2
Timer control register W2
R/W
at RAM back-up : state retained
at reset : 0000
2
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
P1
2
(I/O)/CNTR input (Note 3)
P1
2
(input)/CNTR input/output (Note 3)
Not used
Not used
CNTR output selection bit
P1
2
/CNTR function selection bit
0
1
0
1
0
1
0
1
Timer control register W6
R/W
at RAM back-up : state retained
at reset : 0000
2
Notes 1:
R
represents read enabled, and
W
represents write enabled.
2: This function is valid only when the timer 1 count start synchronization circuit is selected.
3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.
Q1
3
Q1
2
A-D control register Q1
A-D operation mode selection bit
Not used
Analog input pin selection bits
at reset : 0000
2
at RAM back-up : state retained
0
1
0
1
Q1
1
0
0
1
1
A-D conversion mode
Comparator mode
This bit has no function, but read/write is enabled.
Selected pins
A
IN0
A
IN1
Not available
Not available
Q1
0
0
1
0
1
R/W
Q1
1
Q1
0
W2
3
W2
2
W2
1
W2
0
W6
3
W6
2
W6
1
W6
0
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