參數(shù)資料
型號： M34501M4
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機的CMOS
文件頁數(shù)： 24/113頁
文件大小： 1252K
代理商： M34501M4
24
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TIMERS
The 4501 Group has the following timers.
Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a set-
ting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to
“
1,
”
new data is loaded from the reload reg-
ister, and count continues (auto-reload function).
Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency divid-
ing ratio (n). An interrupt request flag is set to
“
1
”
after every n
count of a count pulse.
Fig. 21 Auto-reload function
Count source
Instruction clock
Prescaler output (ORCLK)
Timer 1 underflow
Prescaler output (ORCLK)
CNTR input
System clock
Instruction clock
Structure
Frequency divider
8-bit programmable
binary down counter
(link to INT input)
8-bit programmable
binary down counter
16-bit fixed dividing
frequency binary down
counter
Circuit
Prescaler
Timer 1
Timer 2
16-bit timer
Use of output signal
Timer 1 and 2 count sources
Timer 2 count source
CNTR output
Timer 1 interrupt
CNTR output
Timer 2 interrupt
Watchdog timer
(The 16th bit is counted twice)
Frequency
dividing ratio
4, 16
1 to 256
1 to 256
65536
Control
register
W1
W1
W2
W2
The 4501 Group timer consists of the following circuits.
Prescaler : frequency divider
Timer 1 : 8-bit programmable timer
Timer 2 : 8-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
16-bit timer
Prescaler and timers 1 and 2 can be controlled with the timer con-
trol registers W1, W2 and W6. The 16-bit timer is a free counter
which is not controlled with the control register.
Each function is described below.
Table 9 Function related timers
F
F
1
6
n
00
16
n
:
C
o
Count starts
u
n
t
e
r
i
n
i
t
i
a
l
v
a
l
u
e
Reload
Reload
1st underflow
2nd underflow
n
+
1
c
o
u
n
t
n
+
1
c
o
u
n
t
T
i
m
e
An interrupt occurs or
a skip instruction is executed.
T
r
i
e
m
q
e
u
r
s
i
t
n
t
l
e
a
r
g
r
u
p
t
e
f
T
e
c
o
n
t
e
n
t
s
o
f
c
o
u
n
t
e
r
“
1
”
“
0
”
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