參數(shù)資料
型號(hào)： M34280E1GP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 605K
代理商： M34280E1GP
12
MITSUBISHI MICROCOMPUTERS
4280 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
Table 4 Control registers related to timer
V12
V11
V10
Timer control register V1
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
Carrier output (CARRY)
Bit 5 of watchdog timer (WDT)
Stop (Timer 1 state retained)
Operating
0
1
0
1
0
1
Carrier wave output auto-control bit
Timer 1 count source selection bit
Timer 1 control bit
at reset : 0002
W
at RAM back-up : 0002
Note: “W” represents write enabled.
(4) Timer 1 underflow flag (T1F)
Timer 1 underflow flag is set to “1” when the timer 1 underflows.
The state of this flag can be examined with the skip instruction
(SNZT1).
T1F flag is cleared to “0” when the next instruction is skipped
with a skip instruction.
(1) Control register related to timer
Timer control register V1
Register V1 controls the timer 1 count source and auto-
control function of carrier wave output from port CARR by
timer 1. Set the contents of this register through register A
with the TV1A instruction.
(2) Precautions
Note the following for the use of timers.
Count source
Stop timer 1 counting to change its count source.
Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
(3) Timer 1
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1).
When timer is stopped, data can be set simultaneously in timer
1 and the reload register (R1) with the T1AB instruction.
When timer is operating, data can be set to only reload register
R1 with the T1AB instruction.
When setting the next count data to reload register R1 at
operating, set data before timer 1 underflows.
Timer 1 starts counting after the following process;
set data in timer 1,
select the count source with the bit 1 of register V1, and
set the bit 0 of register V1 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 underflow flag (T1F) is set to “1,” new data is loaded
from reload register R1, and count continues (auto-reload
function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B. When
reading the data, stop the counter and then execute the TAB1
instruction.
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