10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
10-179
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
Figure 10.8.11 Reload 0 and Reload 1 Register Updates in PWM Output Mode (For 0% or 100% Duty-Cycle Wave Output)
H'FFFF
FFFF
H'1000
FFFF
H'9000
(a) When reload register updates take effect in the current period (reflected in the next period)
Timing at which reload 0
register is updated
Operation by new reload value written
Reload 0 register
Reload 1 register
F/F output
Write to reload 1
Write to reload 0
(Reload 1 data latched)
PWM period latched and timing at which reload 1 buffer is updated
Count clock
Reload 0 register
Reload 1 register
Counter
Interrupt due
to underflow
F/F output
Reload 1 buffer
H'0FFF
FFFF
H'9000
H'2000
H'0FFE
H'9000
(b) When reload register updates take effect in the next period (reflected one period later)
Operation by old reload value
Note: This diagram does not show detailed timing information.
Timing at which reload 0 register is updated
Reload 0 register
Reload 1 register
F/F output
Write to reload 1
Write to reload 0
(Reload 1 data latched)
PWM period latched
Count clock
Reload 0 register
Reload 1 register
Counter
Interrupt due
to underflow
F/F output
Reload 1 buffer
H'0001
H'FFFF
H'1000
FFFF
H'2000
FFFF
H'9000
H'1000
H'2000
FFFF
H'9000
8FFF
H'0000
H'2000
H'9000
H'0001
H'FFFF
H'1000
H'0FFF
H'2000
FFFF
H'9000
H'1000
H'2000
FFFF
H'9000
H'0FFE
H'0000
H'2000
Old PWM output period
New PWM
output period
New PWM output period
Enlarged
view
Enlarged
view
Old PWM
output period
Old PWM output period