DMAC
9-20
9
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
DMA7 Channel Control Register 0 (DM7CNT0)
<Address: H’0080 0438>
123456
b7
b0
SADSL7 DADSL7
MDSEL7 TREQF7
REQSL7
TENL7
TSZSL7
00000000
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL7
0: Normal mode
R
W
DMA7 transfer mode select bit
1: Ring buffer mode
1
TREQF7
0: Transfer not requested
R(Note 1)
DMA7 transfer request flag bit
1: Transfer requested
2, 3
REQSL7
00: Software start
R
W
DMA7 transfer request source select bit
01: SIO2_TXD (transmit buffer empty)
10: CAN0_S1/S30
11: Extended DMA7 transfer request source select
(DMA7 Channel Control Register 1)
4
TENL7
0: Disable transfer
R
W
DMA7 transfer enable bit
1: Enable transfer
5
TSZSL7
0: 16 bits
R
W
DMA7 transfer size select bit
1: 8 bits
6
SADSL7
0: Fixed
R
W
DMA7 source address direction select bit
1: Increment
7
DADSL7
0: Fixed
R
W
DMA7 destination address direction select bit
1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
9.2 DMAC Related Registers