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Clock Generating Circuit
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
43
Figure 1.8.4. Clock control registers 0 and 1
System clock control register 0 (Note 1)
Symbol
CM0
Address
0006
16
When reset
08
16
Bit
Function
Bit symbol
b7
b6
b5
b4
b3 b2
b1
b0
3
0 1 : f
C
output (Note 3)
1 0 : f
8
output (Note 3)
1 1 : f
32
output (Note 3)
0 : Do not stop f
1
, f
8
, f
32
in wait mode
1 : Stop f
1
, f
8
, f
32
in wait mode
0 : LOW
1 : HIGH
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
Clock outpname
select bit (Note 2)
WAIT peripheral function
clock stop bit
X
CIN
-X
COUT
drive capacity
select bit (Note 4)
Port X
C
select bit
0 : I/O port
1 : X
CIN
-X
COUT
generation
0 : On
1 : Off (Note 7)
0 : Watchdog timer interrupt
1 : Reset (Note 8)
Main clock (X
IN
-X
OUT
)
stop bit (Note 5, 6)
Watchdog timer function
select bit
System clock select bit
(Note 9)
0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: When outputting BCLK (bit 7 of processor mode register 0 is "0"), set these bits to "00". When
outputting ALE to P5
3
(bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". The
port P5
3
function is not selected even when you set "00" in microprocessor or memory expansion
mode and bit 7 of the processor mode register 0 is "1".
Note 3: When selecting f
C
, f
8
or f
32
in single chip mode, must use P5
7
as input port.
Note 4: Changes to “1” when shifting to stop mode or reset.
Note 5: When entering power saving mode, main clock stops using this bit. When returning from stop
mode and operating with X
IN
, set this bit to “0”.
Note 6: When this bit is "1", X
OUT
is "H". Also, the internal feedback resistance remains ON, so X
IN
is pulled
up to X
OUT
("H" level) via the feedback resistance.
Note 7: When the main clock is stopped, the main clock division register (address 000C
16
) is set to the
division by 8 mode.
Note 8: When "1" has been set once, "0" cannot be written by software.
Note 9: To set CM07 "1" from "0", first set CM04 to "1", and an oscillation of sub clock is stable. Then set
CM07. Do not set CM04 and CM07 simultaneously. Also, to set CM07 "0" from "1", first set CM05
to "1", and an oscillation of main clock is stable. Then set CM07.
System clock control register 1 (Note 1)
Symbol
CM1
Address
0007
16
When reset
20
16
Bit
Function
Bit symbol
b7
0
b6
0
b5
b4 b3
0
b2
0
b1
0
b0
CM10
All clock stname
(Note 3)
0 : Clock on
1 : All clocks off (stop mode) (Note 4)
Note 1: Set bit 0 of the protect register (address 000A
16
) to
“1” before writing to this register.
Note 2: Changes to
“1” when shifting from high-speed or middle-speed mode to stop mode or reset.
This bit is remained in low speed or low power dissipation mode.
Note 3: When this bit is "1", X
OUT
is "H", and the internal feedback resistance is disabled. X
CIN
and
X
COUT
are high-inpedance.
Note 4: When the main clock is stopped, the main clock division register (address 000C
16
) is set to the
division by 8 mode.
CM15
X
IN
-X
OUT
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
Reserved bit
Always set to
“0”
0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Reserved bit
Always set to
“0”
CM06