deveopmen
Bus Settings
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
30
P0
0
to P0
7
I/O port
Data bus
Data bus
Data bus
Data bus
I/O port
I/O port
CS1 or CS2 : multiplexed
bus, and the other :
separate bus
Separate bus
All space multiplexed
bus
Single-chip
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
Data bus width
BYTE pin level
“01”, “10”
“00”
“11” (Note 1)
All external
area is 8 bits
Some external
area is 16 bits
All external
area is 8 bits
Some external
area is 16 bits
Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in
microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Note 2: Address bus in separate bus configuration.
Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1.
Note 4: When you have selected use of the DRAM controller and you access the DRAM area, these are CASL, CASH, DW, and
BCLK outputs.
Note 5: The CS signal and address bus selection are set by the external area mode.
Processor
mode
Multiplexed
bus space
select bit
CS (chip select) or address bus (A
23
)
(For details, refer to “Bus control”) (Note 5)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”) (Note 3,4)
P1
0
to P1
7
port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port I/O
P2
0
to P2
7
I/O port
Address bus
/data bus
(Note 2)
Address bus
/data bus
(Note 2)
Address bus
Address bus
Address bus
/data bus
Address bus
/data bus
P4
0
to P4
3
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
I/O port
P4
4
to P4
6
I/O port
CS (chip select) or address bus (A
23
)
(For details, refer to “Bus control”) (Note 5)
P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port
HLDA(Note 3)
HLDA(Note 3)
HLDA(Note 3)
HLDA(Note 3)
HLDA(Note 3) HLDA(Note 3)
P5
5
I/O port
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
P5
6
I/O port
RAS (Note 3)
RAS (Note 3)
RAS (Note 3)
RAS (Note 3)
RAS (Note 3) RAS (Note 3)
P5
7
I/O port
RDY
RDY
RDY
RDY
RDY
RDY
P3
0
to P3
7
I/O port
Address bus
Address bus
/data bus
(Note 2)
Address bus
Address bus
Address bus
Address bus
/data bus
Table 1.7.3. Each processor mode and port function