deveopmen
UARTi Special Mode Register
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
153
Selector
I/O
Timer
delay
UART2
Reception register
UART2
External clock
Arbitration
Start condition detection
Stop condition detection
Falling edge
detection
UART2
transmission/NACK
interrupt request
UART2 reception/ACK
interrupt request
DMAi request
9th pulse
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
1
of the direction register.
L-synchronous
output enabling bit
Bus collision/start, stop
condition detection
interrupt request
Bus collision
detection
UART2
Filter
I/0
Noize
P7
0
/TXD
2
/SDA
P7
1
/RXD
2
/SCL
CLK
control
Internal clock
UART2
IICM=1
Serector
UART2
IICM=0
I/0
Timer
P7
2
/CLK
2
Data register
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
R
IICM=1
IICM=0
SDHI
IICM=1
IICM=0
IICM=1 and
IICM2=0
IICM=0
IICM=1
S
RQ
Bus
busy
IICM=1
IICM=0
ALS
R
S
SWC
Falling edge of 9th pulse
IICM=1 and
IICM2=0
IICM=0 or IICM2=1
IICM=0 or
IICM2=1
SWC2
To DMAi
To DMAi
Selector
Transmission register
UART2
Noize
Figure 1.20.2. Functional block diagram for I
2
C mode
Figure 1.20.2 is a block diagram of the IIC bus interface.
To explain the control bit of the IIC bus interface, UART2 is used as an example.
UART2 Special Mode Register (Address 0337
16
)
Bit 0 is the IIC mode select bit. When set to “1”, ports P7
0
, P7
1
and P7
2
operate respectively as the
SDA2 data transmission-reception pin, SCL2 clock I/O pin and port P7
2
. A delay circuit is added to
SDA2 transmission output, therefore after SCL2 is sufficiently L level, SDA2 output changes. Port P7
1
(SCL2) is designed to read pin level regardless of the content of the port direction register. SDA2
transmission output is initially set to port P7
0
in this mode. Furthermore, interrupt factors for the bus
collision detection interrupt, UART2 transmission interrupt and UART2 reception interrupt change
respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and
acknowledge detection interrupt.