deveopmen
Processor Mode
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
26
Figure 1.6.2. Processor mode register 1
Processor mode register 1 (Note 1) :Flash memory version
Symbol
PM1
Address
0005
16
When reset
00
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
0
b2
b1
b0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
3
/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
ALE pin select bit (Note 3)
0 0 : No ALE
0 1 : P5
3
/BCLK (Note 4)
1 0 : P5
6
/RAS
1 1 : P5
4
/HLDA
b5 b4
PM15
PM14
Reserved bit
Must always be set to “0”
W
R
AA
AA
AA
AA
Reserved bit
Must always be set to “1”
PM12
Internal memory wait bit
0 : No wait state
1 : Wait state inserted
External memory area
mode bit (Note 3)
0 0 : Mode 0 (P4
4
to P4
7
: A
20
to A
23
)
0 1 : Mode 1 (P4
4
: A
20
,
P4
5
to P4
7
: CS2 to CS0)
1 0 : Mode 2 (P4
4
, P4
5
: A
20
, A
21
,
P4
6
, P4
7
: CS1, CS0)
1 1 : Mode 3 (Note 2)
(P4
4
to P4
7
: CS3 to CS0)
b1 b0
PM11
PM10
Processor mode register 1 (Note 1) :Mask ROM version
Symbol
PM1
Address
0005
16
When reset
00
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
0
b2
b1
b0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
3
/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
ALE pin select bit (Note 3)
0 0 : No ALE
0 1 : P5
3
/BCLK (Note 4)
1 0 : P5
6
/RAS
1 1 : P5
4
/HLDA
b5 b4
PM15
PM14
Reserved bit
Must always be set to “0”
W
R
AA
AA
AA
AA
Nothing is assinged. When read, the content is indeterminate.
PM12
Internal memory wait bit
0 : No wait state
1 : Wait state inserted
External memory area
mode bit (Note 3)
0 0 : Mode 0 (P4
4
to P4
7
: A
20
to A
23
)
0 1 : Mode 1 (P4
4
: A
20
,
P4
5
to P4
7
: CS2 to CS0)
1 0 : Mode 2 (P4
4
, P4
5
: A
20
, A
21
,
P4
6
, P4
7
: CS1, CS0)
1 1 : Mode 3 (Note 2)
(P4
4
to P4
7
: CS3 to CS0)
b1 b0
PM11
PM10