deveopmen
Serial I/O
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
130
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
UART1 internal/external clock select bit (bit 3 at address 0368
16
) = “0”.
UART transmit/receive control register 2
Symbol
UCON
Address
0370
16
When reset
X0000000
2
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
A
R
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
0 :
Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
RCSP
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
UART1 continuous
receive mode enable bit
UART1 transmit
interrupt cause select bit
0 :
Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS
U1IRS
U0RRM
U1RRM
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
A
A
A
A
A
A
A
AA
AA
AA
UARTi special mode register
Symbol
UiSMR (i=2 to 4)
Address
When reset
00
16
0337
16
, 0327
16
, 02F7
16
b7
b6
b5
b4
b3 b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
ABSCS
ACSE
SSS
IIC mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected
SCLL sync output
enable bit
Bus collision detect
sampling
clock select bit
Arbitration lost detecting
flag control bit
0 : Normal mode
1 : IIC mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
LSYN
0 : Ordinary
1 : Falling edge of RxDi
0 : Disabled
1 : Enabled
Transmit start condition
select bit
Must always be “0”
0 : Rising edge of transfer clock
1 : Underflow signal of timer Ai
(Note 2)
Auto clear function
select bit of transmit
enable bit
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Note 1: Nothing but "0" may be written.
Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4
underflow signal.
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Must be fixed to “0”
Must be fixed to “0”
Figure 1.16.10. Serial I/O-related registers (6)