參數(shù)資料
型號： M30240M5-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 68/139頁
文件大?。?/td> 1453K
代理商： M30240M5-XXXFP
34
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
NMI Interrupt
1.2.12.3 Flag changes
When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag
register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to “0” and the
processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the
received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the
flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select
flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not
change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the
case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and
undefined instruction interrupts. Table 1.12 shows how the IPL changes when interrupt requests are
received.
Table 1.12:
Change of IPL state when interrupt request are accepted
1.2.13 NMI Interrupt
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI
interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P85 register (bit
5 at address 03F016).
This pin cannot be used as a normal port input.
Notes:
1. When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI
interrupt is non-maskable, it cannot be disabled.
2.
When the NMI pin input is “L”, do not set the microcomputer in stop mode or wait mode. The NMI
interrupt is triggered by the falling edge, so the “L” level does not need to be maintained longer than
necessary.
Interrupt
Change of IPL
Reset
Level 0 (0002), is set
NMI
Level 7 (1112), is set
DBC
Does not change
Watchdog timer
Level 7 (1112), is set
Single step
Does not change
Address match
Does not change
Software interrupt
Does not change
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PDF描述
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