參數(shù)資料
型號(hào): M30100
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 65/164頁(yè)
文件大?。?/td> 3302K
代理商: M30100
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deveopment
Tentative Specifications REV.E1
Timer X
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
64
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.3) Figure 1.14.6
shows the Timer X mode register in timer mode.
Item
Specification
Count source
Count operation
f
1
, f
8
, f
32
, f
C32
Down count
When the timer underflows, it reloads the reload register contents before continuing
counting
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start flag is set (=1)
Count start flag is reset (=0)
Interrupt request generation timing
When Timer X underflows [Timer X interruption]
CNTR0 pin function
Programmable I/O port, or CNTR0 interrupt input pin
TX
OUT
pin function
Programmable I/O port
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Divide ratio
Count start condition
Count stop condition
Table 1.14.3. Specifications of timer mode
Timer X mode register
Symbol
TXMR
Address
008B
16
When reset
00000000
2
Bit name
Function
Bit symbol
W
R
b7
b6 b5
b4
0
b3
b2
b1 b0
0
b1 b0
TXMOD2
TXS
TXMOD1
R0EDG
TXMOD0
TXOCNT
Invalid in timer mode.
When write, set "0". When read, this contents is indeteminate.
Operation mode
select bit 0, 1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Timer X count
start flag
0 : Stops counting
1 : Starts counting
0 : In timer mode, set to "0"
0
0
0 : In timer mode, set to "0"
CNTR0 polarity
switching bit
0 : Rising edge
1 : Falling edge
(Note 1)
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
TXEDG
TXUND
Invalid in timer mode.
When write, set "0". When read, this contents is indeteminate.
Figure 1.14.6. Timer X mode register in timer mode
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