參數(shù)資料
型號(hào)： M30100
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 39/164頁
文件大?。?/td> 3302K
代理商： M30100
deveopment
Tentative Specifications REV.E1
Interrupts
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
38
Interrupt source
Vector table addresses
Address (L) to address (H)
FFFDC
16
to FFFDF
16
FFFE0
16
to FFFE3
16
FFFE4
16
to FFFE7
16
Remarks
Undefined instruction
Overflow
BRK instruction
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF
16
, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
Single step (Note)
Oscillation stop detection/
watchdog timer
DBC (Note)
UART0 receive (Note)
Reset
FFFE8
16
to FFFEB
16
FFFEC
16
to FFFEF
16
FFFF0
16
to FFFF3
16
FFFF4
16
to FFFF7
16
FFFF8
16
to FFFFB
16
FFFFC
16
to FFFFF
16
Do not use
Do not use
Table 1.12.1. Interrupt and fixed vector address
Note: Interrupts used for debugging purposes only.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.12.2 shows format for
specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC
16
to FFFFF
16
. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.12.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Figure 1.12.2. Format for specifying interrupt vector addresses
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