參數(shù)資料
型號： M30100
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 22/164頁
文件大?。?/td> 3302K
代理商： M30100
deveopment
Tentative Specifications REV.E1
Clock Generating Circuit
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
21
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After reset, oscillation starts. The clock
can be stopped using the main clock stop bit (bit 5 at address 0006
16
). Stopping the clock reduces the
power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the X
OUT
pin
can be reduced using the X
IN
-X
OUT
drive capacity select bit (bit 5 at address 0007
16
). Reducing the drive
capacity of the X
OUT
pin reduces the power dissipation. This bit changes to “1” when shifting from high-
speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissi-
pation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 0006
16
), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 0006
16
). However, be sure that
the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the X
COUT
pin
can be reduced using the X
CIN
-X
COUT
drive capacity select bit (bit 3 at address 0006
16
). Reducing the
drive capacity of the X
COUT
pin reduces the power dissipation. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU. The clock source for BCLK is as follows: (1) the clock derived
by dividing the main clock by 1, 2, 4, 8, or 16, (2) f
C
, or (3) the clock derived by dividing the clock supplied
by the ring oscillator circuit (f
RING
) by 1, 2, 4, 8 or 16. After reset, the BCLK is derived by dividing the f
RING
by 8. When using an external RC oscillator circuit for the main clock, 1 division of the main clock cannot
be selected as BCLK.
The main clock division select bit 0(bit 6 at address 0006
16
) changes to “1” when shifting from high-
speed/medium-speed mode to stop mode and at reset. When shifting from low-speed/low power dissipa-
tion mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock
a. f
1
, f
8
, f
32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped as follows: (i) by stopping the main clock or (ii) by executing an
WAIT instruction after setting the WAIT peripheral function clock stop bit (bit 2 at 0006
16
) to “1”. When
using an external RC oscillator circuit for the main clock, f
1
cannot be selected as the operation clock
of some peripheral devices.
b. f
AD
This clock has the same frequency as the main clock and is used in A-D conversion.
(5) f
C32
This clock is derived by dividing the sub-clock by 32. It is used for the timer 1, timer X, timer Y and timer
Z counts. Figure 1.8.6 shows the block diagram of fc
32
.
(6) f
C
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
(7) f
RING
This clock is supplied by the ring oscillator circuit. In the ring oscillator mode, the clock divided by the
division ratio selected with the main clock division select bit 0 and bit 1(bit 6 at address 0006
16
, and bit 6
and bit 7 at address 0007
16
) is supplied as BCLK. Immediately after reset, 8 divisions of this clock is
supplied as BCLK. The ring oscillator oscillation can be set to BCLK when oscillation stop is detected or
with the main clock switching bit (bit 2 at address 000C
16
).
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