參數(shù)資料
型號(hào)： M30100
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 30/164頁
文件大小： 3302K
代理商： M30100
Power Control
deveopment
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
29
CM07=“0“ (Note 1)
CM06=“1”
CM04=“0”
CM04=“1”
(Notes 1, 3)
CM04=“0”
BCLK: f(X
IN
)/8
CM07=“0” CM06=“1”
CM06=“1”
BCLK: f(
RING
)/8
CM07=“0”
CM06=“1”
CM22=“1”
BCLK: f(
RING
)/8
CM07=“0” CM06=“1”
BCLK: f(
RING
)/2
BCLK: f(
RING
)
CM07=“0” CM06=“0”
CM22=“1”
CM22=“0” (Note 1)
BCLK: f(
RING
)/16
BCLK: f(
RING
)/4
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Low-speed mode
High-speed mode
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
BCLK : f(X
IN
)/2
“
0
”
“
0
”
CM07 =
“
0
”
CM06 =
“
1
”
(divided-by-2 mode)
BCLK : f(X
IN
)/16
“
0
”
“
0
”
CM07 =
“
1
”
CM06 =
“
1
”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
“
0
”
“
0
”
CM07 =
“
1
”
CM06 =
“
0
”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
“
0
”
“
0
”
CM07 =
“
0
”
CM06 =
“
0
”
BCLK : f(X
IN
)/8
Medium-speed mode
(divided-by-8 mode)
CM07 =
“
0
”
CM06 =
“
1
”
High-speed mode
BCLK : f(X
IN
)/2
“
0
”
“
0
”
CM07 =
“
0
”
CM06 =
“
1
”
Medium-speed mod
(divided-by-2 mode)
BCLK : f(X
IN
)/16
“
0
”
“
0
”
CM07 =
“
1
”
CM06 =
“
1
”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
“
0
”
“
0
”
CM07 =
“
1
”
CM06 =
“
0
”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
“
0
”
“
0
”
CM07 =
“
0
”
CM06 =
“
0
”
BCLK : f(X
CIN
)
CM07 =
“
1
”
CM06 =
“
1
”
BCLK : f(X
CIN
)
CM07 =
“
1
”
CM06 =
“
1
”
Main clock is oscillating
Sub clock is oscillating
“
0
”
CM07 =
CM07 =
“
1
”
CM06 =
“
1
”
(Note 2,5)
“
0
”
“
0
”
(Note 1)
CM07 =
“
1
”
CM05 =
“
0
”
CM05 =
“
1
”
CM04 =
“
0
”
CM04 =
“
1
”
“
0
”
CM06 =
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 4: Transit in accordance with arrow.
Note 5: Before switching BCLK to other from the main clock, divide the main
clock by 8 for safty purposes to switch BCLK to the main clock again.
Main clock is oscillating
Ring oscillator mode (divided-by-8 mode)
Main clock is stopped
Sub clock is stopped
CM05 =
“
0
”
CM05 =
“
1
”
8-division mode
1-division mode (Note 3)
2-division mode (Note 3)
16-division mode (Note 3)
4-division mode (Note 3)
“
0
”
“
0
”
“
1
”
“
1
”
CM07=
“
1
”
CM06=
“
0
”
“
0
”
“
0
”
CM07=
“
1
”
CM06=
“
1
”
CM16=
“
1
”
CM17=
“
1
”
“
0
”
“
0
”
CM07=
“
1
”
CM06=
“
1
”
CM16=
“
0
”
CM17=
“
1
”
Figure 1.9.2. Clock transition (2)
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