參數(shù)資料
型號： M29W004B
廠商： 意法半導(dǎo)體
英文描述： 4Mbit (512Kb x8, Boot Block) Low Voltage Single Supply Flash Memory(4Mb閃速存儲(chǔ)器)
中文描述： 的4Mb（512KB的× 8，引導(dǎo)塊）低電壓單電源閃存（4Mb的閃速存儲(chǔ)器）
文件頁數(shù)： 11/30頁
文件大?。?/td> 199K
代理商： M29W004B
Toggle Bit (DQ2).
This toggle bit, together with
DQ6, can be used to determine the device status
duringthe Eraseoperations.It can alsobe usedto
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend.During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
duringprogramoperationand whenerase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5).
This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
thememoryblock.In caseof anerrorinblockerase
or program,the blockin whichtheerror occuredor
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pearifa usertriesto programa’1’toa locationthat
is previouslyprogrammedto ’0’. OtherBlocksmay
stillbe used.TheerrorbitresetsafteraRead/Reset
(RD)instruction. In caseof successof Program or
Erase, the error bit will be set to ’0’.
EraseTimer Bit (DQ3).
This bit is setto ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
periodis finished,after 50
μ
s to 90
μ
s, DQ3 returns
to ’1’.
Coded Cycles
The two Coded cyclesunlockthe CommandInter-
face.They are followedby an input commandor a
confirmationcommand. The Coded cycles consist
ofwritingthe dataAAhat address5555hduringthe
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
2AAAh.A0 toA14are valid,otheraddresslinesare
’don’tcare’.The Codedcycleshappenon first and
second cycles of the command write or on the
fourthand fifth cycles.
Instructions
SeeTable 8.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
commandF0h.Itcanbeoptionallyprecededby the
twoCodedcycles.Subsequentreadoperationswill
read the memory array addressed and output the
data read. A wait state of 10
μ
s is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction.
This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 5555h
forcommandset-up.Asubsequentread willoutput
the manufacturercode and the device code or the
block protectionstatus depending on the levels of
A0 and A1 The manufacturercode, 20h, is output
when the addresseslines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is output when A0 is Highwith A1 Low.
The AS instruction also allowsaccess to the block
protectionstatus.After givingtheASinstruction,A0
andA6 are setto V
IL
withA1at V
IH
, whileA13-A18
definetheaddressof theblockto beverified.Aread
in these conditions will output a 01h if the block is
protectedand a 00h if the blockis not protected.
Program (PG) Instruction.
This instruction uses
four write cycles. The Program command A0h is
writtento address5555honthethirdcycleaftertwo
Codedcycles. Afourthwrite operationlatchesthe
Addresson thefallingedge of W orE and theData
to be written on the rising edge and starts the
P/E.C.Readoperationsoutputthe StatusRegister
bits after the programming has started. Memory
programmingis madeonlyby writing ’0’in placeof
’1’.StatusbitsDQ6andDQ7determineif program-
mingison-goingandDQ5allowsverificationof any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dressbeing programmed.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in EraseSuspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Note:
1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Table10. Pollingand Toggle Bits
11/30
M29W004T M29W004B
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