參數(shù)資料
型號: M12L64164A-5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 4.5 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁數(shù): 6/45頁
文件大小: 831K
代理商: M12L64164A-5BG
ES MT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
6/45
AC CHARACTERISTICS
(AC operating condition unless otherwise noted)
-5
-6
-7
PARAMATER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
CAS latency = 3
5
6
7
CLK cycle time
CAS latency = 2
t
CC
10
-
10
-
10
-
ns
1
CAS latency = 3
-
4.5
-
5.5
-
6
CLK to valid
output delay
CAS latency = 2
t
SAC
-
6
-
6
-
6
ns
1,2
CAS latency = 3
2.0
-
2.5
-
2.5
-
Output data
hold time
CAS latency = 2
t
OH
2.0
-
2.5
-
2.5
-
ns
2
CLK high pulsh width
t
CH
2.5
-
2.5
-
2.5
-
ns
3
CLK low pulsh width
t
CL
2.5
-
2.5
-
2.5
-
ns
3
Input setup time
t
SS
1.5
-
1.5
-
1.5
-
ns
3
Input hold time
t
SH
1
-
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
0
-
0
-
0
-
ns
2
CAS latency = 3
-
5.5
-
5.5
-
6
CLK to output
in Hi-Z
CAS latency = 2
t
SHZ
-
5.5
-
6
-
6
ns
-
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
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