參數(shù)資料
型號: M12L64164A-5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 4.5 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁數(shù): 16/45頁
文件大小: 831K
代理商: M12L64164A-5BG
ES MT
Self refresh entry command
(CS ,RAS ,CAS , CKE = Low ,
WE
= High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the M12L64164A exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
(CS ,
WE
= Low,RAS ,CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
(CS = Low ,RAS ,CAS ,
WE
= High)
This command is not a execution command. No operations begin or terminate by
this command.
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
16/45
CLK
CKE
A12, A13
(Bank select)
A10
Add
CLK
CKE
(Bank select)
A10
Add
H
Fig. 7 Self refresh entry
command
Fig. 8 Burst stop command
CLK
CKE
A12, A13
(Bank select)
A10
Add
H
Fig. 9 No operation
CS
RAS
WE
CAS
CS
RAS
WE
CAS
CS
RAS
WE
CAS
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