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參數(shù)資料
| 型號： | M12L64164A-5BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 4.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VBGA-54 |
| 文件頁數(shù)： | 5/45頁 |
| 文件大?。?/td> | 831K |
| 代理商： | M12L64164A-5BG |
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ES MT
AC OPERATING TEST CONDITIONS
(VDD = 3.3V
±
0.3V
，
TA = 0 to 70 C
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
5/45
)
PARAMETER
VALUE
UNIT
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
-5
-6
-7
UNIT
NOTE
Row active to row active delay
t
RRD(min)
10
12
14
ns
1
RAS to CAS delay
Row precharge time
t
RCD(min)
15
18
20
ns
1
t
RP(min)
15
18
20
ns
1
t
RAS(min)
38
40
42
ns
1
Row active time
t
RAS(max)
100
us
@ Operating
@ Auto refresh
t
RC(min)
53
58
63
ns
1
Row cycle time
t
RFC(min)
55
60
70
ns
1,5
Last data in to col. address delay
t
CDL(min)
1
CLK
2
Last data in to row precharge
t
RDL(min)
2
CLK
2
Last data in to burst stop
t
BDL(min)
1
1
CLK
CLK
2
3
Col. address to col. address delay
t
CCD(min)
CAS latency = 3
2
Number of valid
Output data
CAS latency = 2
1
ea
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
Output
870
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
50pF
Z0 =50
50pF
50
Vtt = 1.4V
3.3V
1200
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L64164A-5BG2Y | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks |
| M12L64164A-5BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L64164A-5TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L64164A-5TG2Y | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks |
| M12L64164A-5TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
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