參數(shù)資料
型號: M12L64164A-5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 4.5 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁數(shù): 26/45頁
文件大小: 831K
代理商: M12L64164A-5BG
ES MT
Current
State
Read with
Auto
Precharge
Row
Activating
Refreshing
Mode
Register
Accessing
Abbreviations :
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
26/45
CS
RAS CAS
WE
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
BA
ADDR
ACTION
Note
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CA
RA
NOP
Idle after tRP
NOP
Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after tRPL
ILLEGAL
NOP
Row Active after tRCD
NOP
Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after tRFC
NOP
Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after 2clocks
NOP
Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
4
2
2
2
2
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
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