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參數(shù)資料
| 型號： | M12L16161A-7TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50 |
| 封裝： | 0.400 X 0.825 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 714K |
| 代理商： | M12L16161A-7TG |
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ES MT
SIMPLIFIED TRUTH TABLE
M12L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2005
Revision
:
2.4
11/30
COMMAND
Mode Register Set
Auto Refresh
CKEn-1
H
CKEn
X
H
L
CS
L
RAS
L
CAS
L
WE
L
DQM BA A10/AP A9~A0 Note
X
OP CODE
Register
1,2
3
3
3
3
4
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self Refresh
Exit
L
H
X
X
Bank Active & Row Addr.
H
X
X
V
Row Address
L
Auto Precharge Disable
Read &
Column Address
Auto Precharge Enable
Auto Precharge Disable
H
X
L
H
L
H
X
V
H
L
H
Column
Address
(A0~A7)
Column
Address
(A0~A7)
4,5
4
Write & Column
Address
Burst Stop
Auto Precharge Enable
H
X
L
H
L
L
X
V
4,5
H
X
L
H
H
L
X
X
6
4
4
7
Bank Selection
Both Banks
V
X
L
H
Precharge
H
X
L
L
H
L
X
X
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
Entry
H
L
X
Precharge Power Down Mode
Exit
L
H
X
X
DQM
H
H
H
V
X
H
L
X
H
X
H
No Operation Command
X
X
X
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks idle state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L2561616A | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-6BG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-6TG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-7BG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-7TG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L16161A-7TG2Q | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks |
| M12L16161A-7TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-8T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161C6TAA | 制造商:ELITE 功能描述:New |
| M12L16161C6TAASQ | 制造商:MOTOROLA 功能描述:NEW |
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