參數(shù)資料
型號(hào): M12L128324A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 100萬× 32位× 4個(gè)銀行同步DRAM
文件頁數(shù): 43/47頁
文件大?。?/td> 794K
代理商: M12L128324A
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
43/47
Self Refresh Entry & Exit Cycle
*Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA 0, BA 1
S el f R ef r es h E n t r y
A u t o R ef r es h
: D o n ' t c a r e
*Not e 2
*Not e 1
t
S S
*No t e 3
*Not e 4
t
R C
m i n
*Not e 6
S e l f R ef r e s h E xi t
H i - Z
H i - Z
*No t e 5
*Not e 7
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
相關(guān)PDF資料
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M12L128324A-6BG 1M x 32 Bit x 4 Banks Synchronous DRAM
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