參數(shù)資料
型號(hào)： M12L128324A
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述： 100萬(wàn)× 32位× 4個(gè)銀行同步DRAM
文件頁(yè)數(shù)： 8/47頁(yè)
文件大?。?/td> 794K
代理商： M12L128324A
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
8/47
Version
Parameter
Symbol
-6
-7
Unit
Note
Col. address to col. address delay
t
CCD(min)
1
CLK
3
CAS latency = 3
2
CAS latency = 2
1
Number of valid
Output data
CAS latency = 1
0
ea
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS
(AC operating condition unless otherwise noted)
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Note
CAS latency = 3
6
7
CAS latency = 2
10
8.6
CLK cycle time
CAS latency = 1
t
CC
20
1000
20
1000
ns
1
CAS latency = 3
-
5.5
-
6
CAS latency = 2
-
6
-
6
CLK to valid
output delay
CAS latency = 1
t
SAC
-
17
-
18
ns
1,2
CAS latency = 3
2
-
2
-
CAS latency = 2
2
-
2
-
Output data
hold time
CAS latency = 1
t
OH
2
-
2
-
ns
2
CLK high pulsh width
t
CH
2
-
2.5
-
ns
3
CLK low pulsh width
t
CL
2
-
2.5
-
ns
3
Input setup time
t
SS
2
-
2
-
ns
3
Input hold time
t
SH
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
1
-
ns
2
CAS latency = 3
-
5.5
-
6
CAS latency = 2
-
6
-
6
CLK to output
in Hi-Z
CAS latency = 1
t
SHZ
-
17
-
18
ns
-
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
相關(guān)PDF資料
PDF描述
M12L128324A-6BG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6TG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L16161A-5TG 512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A-7BG 512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A-7TG 512K x 16Bit x 2Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L128324A_09 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A_1 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A2E 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply
M12L128324A-5BG2E 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply
M12L128324A-6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
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