參數(shù)資料
型號(hào)： EP20K400ERC240-3
廠商： ALTERA CORP
元件分類(lèi)： PLD
英文描述： LOADABLE PLD, PQFP240
封裝： HEAT SINK, POWER, QFP-240
文件頁(yè)數(shù)： 37/65頁(yè)
文件大?。?/td> 781K
代理商： EP20K400ERC240-3
64
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 28. Column IOE Connection to the Interconnect
Advanced I/O Standard Support
The APEX 20KE IOE supports the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, 3.3-V AGP, LVDS, GTL+,
SSTL-3 Class I and II, SSTL-2 Class I and II, and HSTL Class I, II, and III.
The APEX 20KE device contains eight I/O blocks. All blocks support all
standards except LVDS. In addition, one block supports LVDS inputs, and
another block supports LVDS outputs. Each I/O block has its own VCCIO
pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each
block can support a different standard independently. Each block can also
use a separate VREF level, so that each block can support any of the
terminated standards (such as SSTL-3) independently. Within a block,
any one of the terminated standards can be supported. EP20K300E and
larger APEX 20KE devices support the LVDS interface.
When LVDS signals are used within a block, other I/O standards should
not be used within the same block to avoid degrading the high-
performance LVDS signal. An exception can be made for the ClockLock
LOCK
signal, which does not toggle during normal operation. Figure 29
shows the arrangement of the APEX 20KE I/O blocks.
Row Interconnect
Column Interconnect
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow and column interconnect. Each IOE data
and OE signal is driven by local interconnect.
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
IOE
LAB
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
MegaLAB Interconnect
相關(guān)PDF資料
PDF描述
EP20K400ERI240-1 LOADABLE PLD, PQFP240
EP20K400ERI240-2 LOADABLE PLD, PQFP240
EP20K400ERI240-3 LOADABLE PLD, PQFP240
EP20K400FC672-3X LOADABLE PLD, 3.6 ns, PBGA672
EPB5065G 42 MHz, LOW PASS FILTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400FC672-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-1ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA
EP20K400FC672-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA
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