- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377800 > M12L128324A (Elite Semiconductor Memory Technology Inc.) 1M x 32 Bit x 4 Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | M12L128324A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 100萬× 32位× 4個銀行同步DRAM |
| 文件頁數(shù)： | 17/47頁 |
| 文件大?。?/td> | 794K |
| 代理商： | M12L128324A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
17/47
Write command
(CS ,CAS ,
WE
= Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
(CS , CAS = Low, RAS ,
WE
= High)
Read data is available afterCAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
(CS , RAS , CAS = Low,
WE
, CKE = High)
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
During t
RC
period (from refresh command to refresh or activate command), the
M12L128324A cannot accept any other command.
CLK
CLK
CKE
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
BA0, BA1
(Bank select)
A10
A10
Add
Add
CAS
H
H
Col.
Fig. 4 Column address and
write command
Fig. 5 Column address and
read command
CLK
CKE
BA0, BA1
(Bank select)
A10
Add
H
Fig. 6 Auto refresh command
Col.
CS
RAS
WE
CAS
CS
RAS
WE
CAS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L128324A-6BG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L16161A-5TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7TG | 512K x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128324A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A2E | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L128324A-5BG2E | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L128324A-6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。