參數(shù)資料
型號(hào): M12L128324A-7TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86
封裝: 0.400 INCH, LEAD FREE, TSOP2-86
文件頁(yè)數(shù): 41/47頁(yè)
文件大?。?/td> 794K
代理商: M12L128324A-7TG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
41/47
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of t
RDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA1
BA0
RAa
CAa
CAb
RAa
DAa0 DAa1
DAb1
DAb0
DAb2
Row Active
(A-Bank)
W rite
(A-Bank)
Burst Stop
W rite
(A-Bank)
:Don't Care
HIGH
DAa2 DAa3 DAa4
DAb3 DAb4 DAb5
Precharge
(A-Bank)
t
B D L
t
RD L
* Not e 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
相關(guān)PDF資料
PDF描述
M12L128324A 1M x 32 Bit x 4 Banks Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L128324A-7TIG 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L16161A 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A_05 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A_08 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A_1 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM