參數(shù)資料
型號(hào)： M12L128324A-7TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述： 4M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86
封裝： 0.400 INCH, LEAD FREE, TSOP2-86
文件頁(yè)數(shù)： 13/47頁(yè)
文件大?。?/td> 794K
代理商： M12L128324A-7TG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
13/47
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations.All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between V
IL
and V
IH
. During operation with CKE
high all inputs are assumed to be in valid state (low or high) for
the duration of setup and hold time around positive edge of the
clock for proper functionality and Icc specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with
clock, the SDRAM enters the power down mode from the next
clock cycle. The SDRAM remains in the power down mode
ignoring the other inputs as long as CKE remains low. The
power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + t
SS
” before
the high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.
BANK ADDRESSES (BA0~BA1)
This SDRAM is organized as four independent banks of
524,288 words x 32 bits memory arrays. The BA0~BA1 inputs
are latched at the time of assertion of RAS and CAS to
select the bank to be used for the operation. The banks
addressed BA0~BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0~A10)
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0~A11).
The 11 row addresses are latched along with RAS and
BA0~BA1 during bank active command. The 8 bit column
addresses are latched along with CAS ,
WE
and BA0~BA1
during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and
WE
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which require
more than single clock cycle like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
are high , The SDRAM
command decoder so that RAS , CAS ,
WE
and all the
address inputs are ignored.
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE =
“H”, DQM = “H” and the other pins are NOP condition at
the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for both banks of the
devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and
WE
(The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A10
and BA0~BA1 in the same cycle as CS , RAS , CAS
and
WE
going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all
banks are in the idle state. The mode register is divided
into various fields into depending on functionality. The
burst length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
vendor specific options or test mode use A7~A8,
A10/AP and BA0~BA1, A7~A9, A10/AP BA0~BA1,and
all must be set to low for normal SDRAM operation.
Refer to the table for specific codes for various burst
length, burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random
row in an idle bank. By asserting low on RAS and
CS with desired row and bank address, a row access
is initiated. The read or write operation can occur after a
time delay of t
RCD (min)
from the time of bank activation.
t
RCD
is the internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between
bank activate and read or write command should be
calculated by dividing t
RCD (min)
with cycle time of the
clock and then rounding of the result to the next higher
integer.
相關(guān)PDF資料
PDF描述
M12L128324A 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6BG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6TG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L16161A-5TG 512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A-7BG 512K x 16Bit x 2Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L128324A-7TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L16161A 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A_05 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A_08 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
M12L16161A_1 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*