參數(shù)資料
型號: M12L128324A-7TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86
封裝: 0.400 INCH, LEAD FREE, TSOP2-86
文件頁數(shù): 40/47頁
文件大小: 794K
代理商: M12L128324A-7TG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
40/47
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the lable 1,2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
0 1 2 3 4 5 6 7
8
9
10
11
12
13
14 15 16 17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA1
BA0
RAa
CAa
CAb
RAa
QAa0 QAa1
QAb1
QAb0
QAb2
Row Active
(A-Bank)
Read
(A- Bank)
Burst Stop
Read
(A- Bank)
:Don't Car e
HIGH
CL=2
CL=3
QAa2 QAa3 QAa4
QAb3 QAb4 QAb5
QAa0 QAa1
QAb1
QAb0
QAb2
QAa2 QAa3 QAa4
QAb3 QAb4 QAb5
1
1
2
2
Precharge
( A- Bank)
*Not e 2
*Not e 1
*Not e 1
相關PDF資料
PDF描述
M12L128324A 1M x 32 Bit x 4 Banks Synchronous DRAM
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