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參數(shù)資料
| 型號(hào)： | M12L128324A-7BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90 |
| 封裝： | 13 X 8 MM, LEAD FREE, FBGA-90 |
| 文件頁數(shù)： | 27/47頁 |
| 文件大小： | 794K |
| 代理商： | M12L128324A-7BG |
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ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
27/47
FUNCTION TURTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS
RAS
CAS
WE
BA
ADDR
ACTION
Note
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
H
L
X
H
H
L
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
BA
BA
BA
X
X
X
X
NOP
NOP
ILLEGAL
2
2
4
5
5
2
2
3
2
3
3
2
3
2
2
CA, A10/AP ILLEGAL
RA
A10/AP
X
OP code
X
X
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
RA
ILLEGAL
A10/AP
Precharge
X
ILLEGAL
X
NOP (Continue Burst to End
Row Active)
X
NOP (Continue Burst to End
Row Active)
X
Term burst
Row active
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
ILLEGAL
A10/AP
Term burst, Precharge timing for Reads
X
ILLEGAL
X
NOP (Continue Burst to End
Row Active)
X
NOP (Continue Burst to End
Row Active)
X
Term burst
Row active
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
ILLEGAL
A10/AP
Term burst, Precharge timing for Writes
X
ILLEGAL
X
NOP (Continue Burst to End
Precharge)
X
NOP (Continue Burst to End
Precharge)
X
ILLEGAL
CA, A10/AP ILLEGAL
RA, RA10
ILLEGAL
X
ILLEGAL
X
NOP (Continue Burst to End
Precharge)
X
NOP (Continue Burst to End
Precharge)
X
ILLEGAL
CA, A10/AP ILLEGAL
RA, RA10
ILLEGAL
X
ILLEGAL
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
OP code
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L128324A-7TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6BG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L16161A-5TG | 512K x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128324A-7BG2E | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L128324A-7BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L16161A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
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