參數(shù)資料
型號(hào): M12L128324A-7BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝: 13 X 8 MM, LEAD FREE, FBGA-90
文件頁(yè)數(shù): 19/47頁(yè)
文件大小: 794K
代理商: M12L128324A-7BG
ES MT
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
19/47
2. DQM Operation
*Note : 1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
CLK
C M D
CKE
Internal
CLK
DQ(CL 2)
DQ( CL3)
R D
Q2
Q0
Q1
Q3
Q2
Q0
Q1
Q3
D0
D1
D2
D3
D1
D2
D3
D0
W R
Masked by CKE
1) Cl oc k S u s p e n d ed D u r i n g W r i t e ( B L = 4 )
2) C l oc k S u s p e n d e d D u r i n g R ead ( B L= 4 )
Not W ritten
Suspended Dout
CLK
C M D
DQ M
DQ(CL2)
DQ(CL3)
R D
Q0
Q2
Q3
Q1
Q2
Q3
D0
D1
D3
D1
D3
D0
W R
Ma s k e d b y D Q M
Ma s k e d b y D Q M
CLK
C M D
DQ M
DQ(CL2)
DQ(CL3)
CKE
R D
Q0
Q2
Q4
Hi - Z
Hi - Z
Hi - Z
Q6
Q7
Q8
Q5
Q6
Q7
Q1
Q3
Hi - Z
Hi - Z
Hi - Z
Hi - Z
Hi - Z
1 ) W r i t e M a s k ( B L = 4 )
2) R e ad M as k ( B L = 4 )
DQM to Data-in Mask=0
DQM to Data-out Mask= 2
3) D Q M wi t h c l c ok s u s p en d ed ( F u l l P a g e Re ad )
*Not e 2
Internal
CLK
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