參數(shù)資料
型號(hào): M12L128324A-7BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝: 13 X 8 MM, LEAD FREE, FBGA-90
文件頁數(shù): 23/47頁
文件大?。?/td> 794K
代理商: M12L128324A-7BG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
23/47
6. Precharge
.
7. Auto Precharge
1) N o r m a l W r i t e ( B L = 4 )
*Note
:
1. t
RDL
: Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after t
RP
from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
CLK
C M D
DQ
D0
D1
D2
D3
W R
CLK
C M D
DQ(CL2)
Q0
Q1
Q2
Q3
R D
DQ(CL3)
* N o t e 3
Auto Precharge starts
Q0
Q1
Q2
Q3
* N o t e 3
Auto Precharge starts
2) No r m al R ea d ( B L= 4 )
t
RD L
CLK
DQ
D0
D1
D2
D3
W R
t
RD L
*Not e 1
CLK
C M D
C M D
DQ(CL2)
Q0
Q1
Q2
2*No t e 2
1*No t e 2
Q3
R D
PRE
DQ( CL3)
Q0
Q1
Q2
Q3
PRE
1) N o r m a l W r i t e ( B L = 4 )
2) No r m a l R ea d ( B L= 4 )
CL=2
PRE
CL=3
相關(guān)PDF資料
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M12L128324A-7TG 1M x 32 Bit x 4 Banks Synchronous DRAM
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