參數(shù)資料
型號(hào)： M12L128324A-7BG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述： 4M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90
封裝： 13 X 8 MM, LEAD FREE, FBGA-90
文件頁(yè)數(shù)： 11/47頁(yè)
文件大?。?/td> 794K
代理商： M12L128324A-7BG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
11/47
If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
A11
BA0~BA1
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
RFU
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT = 0
BT = 1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved Reserved
A9
Length
1
0
1
Reserved
1
0
1
Reserved Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page Reserved
Full Page Length : 256
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
相關(guān)PDF資料
PDF描述
M12L128324A-7TG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6BG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6TG 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L16161A-5TG 512K x 16Bit x 2Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L128324A-7BG2E 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply
M12L128324A-7BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-7TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-7TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM
M12L16161A 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*