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參數(shù)資料
| 型號： | M12L128324A-7BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA90 |
| 封裝： | 13 X 8 MM, LEAD FREE, FBGA-90 |
| 文件頁數(shù)： | 16/47頁 |
| 文件大?。?/td> | 794K |
| 代理商： | M12L128324A-7BG |
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ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
16/47
COMMANDS
Mode register set command
(CS ,RAS ,CAS ,
WE
= Low)
The M12L128324A has a mode register that defines how the device operates. In
this command, A0 through A10 and BA0~BA1 are the data input pins. After power on,
the mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L128324A cannot accept any
other commands.
Activate command
(CS ,RAS = Low,CAS ,
WE
= High)
The M12L128324A has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 and a row address
selected by A0 through A10.
This command corresponds to a conventional DRAM’s RAS falling.
Precharge command
(CS ,RAS ,
WE
= Low,CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0.
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the M12L128324A can’t accept the activate command to the
precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
CLK
CLK
CKE
CKE
CS
CS
RAS
RAS
WE
WE
BA0, BA1
(Bank select)
A10
A10
Add
Add
CAS
CAS
H
H
Row
Row
Fig. 1 Mode register set
command
Fig. 2 Row address stroble and
bank active command
CLK
CKE
(Bank select)
A10
(Precharge select)
Add
H
Fig. 3 Precharge command
BA0, BA1
(Bank select)
CS
RAS
WE
CAS
相關PDF資料 |
PDF描述 |
|---|---|
| M12L128324A-7TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6BG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L16161A-5TG | 512K x 16Bit x 2Banks Synchronous DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128324A-7BG2E | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L128324A-7BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L16161A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
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