參數(shù)資料
型號: M12L128168A-5TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 4.5 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 8/43頁
文件大?。?/td> 804K
代理商: M12L128168A-5TG
ESMT
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
8/43
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
A13~A12
A11~A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
RFU
W.B.L.
TM
CAS Latency
BT
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT = 0
BT = 1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
Reserved
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
1
0
1
Reserved
1
0
1
Reserved Reserved
1
1
0
Reserved
1
1
0
Reserved Reserved
1
1
1
Reserved
1
1
1
Full Page Reserved
Full Page Length : 512
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single write” function will be enabled.
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