參數(shù)資料
型號: M12L128168A-5TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 4.5 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 37/43頁
文件大小: 804K
代理商: M12L128168A-5TG
ESMT
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
37/43
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
0 1 2 3
4 5 6
7
8
9
10
11
12
13
14 15 16 17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
A13
A12
RAa
CAa
CAb
RAa
QAa0 QAa1
QAb1
QAb0
QAb2
*No t e 1
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
:Don't Care
HIGH
CL=2
CL=3
QAa2 QAa3 QAa4
QAb3 QAb4 QAb5
QAa0 QAa1
QAb1
QAb0
QAb2
QAa2 QAa3 QAa4
QAb3 QAb4 QAb5
1
2
Precharge
(A-Bank)
1
2
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