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參數(shù)資料
| 型號： | M12L128168A-5TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 4.5 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 22/43頁 |
| 文件大?。?/td> | 804K |
| 代理商： | M12L128168A-5TG |
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ESMT
10. Clock Suspend Exit & Power Down Exit
1) Cl o c k S u s p en d ( = Ac t iv e P ow er D o wn ) E x i t
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
22/43
11. Auto Refresh & Self Refresh
*Note
:
1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t
RFC
from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of t
RFC
from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh (4096 cycles) is recommended.
CLK
CKE
Internal
CLK
C M D
R D
t
S S
*Not e 1
CLK
CKE
Internal
CLK
C M D
AC T
t
S S
*Not e 2
NOP
2) P ow er D ow n ( = P r ec h a r g e P o w e r Do w n )
C L K
CM D
PR E
A R
C KE
CM D
t
R P
t
R F C
* N o t e 5
* N o te 4
C L K
CM D
P R E
S R
C KE
C M D
t
R P
t
R F C
* N o te 4
1 ) A u t o R e f r e s h & S e l f R e f r e s h
2 ) S e l f R e f r e s h
* N o t e 3
* N o t e 6
相關PDF資料 |
PDF描述 |
|---|---|
| M12L128168A-6TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128168A-7TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7BG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128168A-5TG2L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:ABSOLUTE MAXIMUM RATINGS |
| M12L128168A-5TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128168A-6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128168A-6BG2L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:ABSOLUTE MAXIMUM RATINGS |
| M12L128168A-6BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
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