參數(shù)資料
型號: M12L128168A-5TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 4.5 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 20/43頁
文件大?。?/td> 804K
代理商: M12L128168A-5TG
ESMT
6. Precharge
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
20/43
.
7. Auto Precharge
*Note
:
1. t
RDL
: Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after t
RP
from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
CLK
C M D
DQ
D0
D1
D2
D3
W R
t
RD L
*Not e 1
CLK
C M D
C M D
DQ(CL2)
Q0
Q1
Q2
Q3
R D
PRE
DQ(CL3)
Q0
Q1
Q2
Q3
PRE
1) N o r m a l W r i t e ( B L = 4 )
2) No r m al R ea d ( B L= 4 )
CL=2
PRE CL=3
*Not e 2
*Not e 2
CLK
C M D
DQ
D0
D1
D2
D3
W R
CLK
C M D
DQ(CL2)
D0
D1
D2
D3
R D
DQ(CL3)
* N o t e 3
Auto Precharge starts
D0
D1
D2
D3
* N o t e 3
Auto Precharge starts
1) N o r m a l W r i t e ( B L = 4 )
2) No r m al R ea d ( B L= 4 )
t
R DL ( m i n )
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