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| 型號(hào)： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 89/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
68
Register Maps
The memory map for the ORSO82G5 core is only part of the full memory map of the ORSO82G5 device. The
ORSO82G5 is an ORCA Series4 based device and thus uses the system bus as a communication bridge. The
ORSO82G5 core register map contained in this data sheet only covers the embedded ASIC core of the device, not
the entire device. The system bus itself, and the generic FPGA memory map, are fully documented in the MPI/Sys-
tem Bus Application Note. As part of the system bus, the embedded ASIC core of an FPSC is located at address
offset 0x30000. The ORSO82G5 embedded core is an eight-bit slave interface on the Series 4 system bus.
Each ORCA device contains a device ID. This device ID is unique to each ORCA device and can be used for device
identication and assist in the system debugging. The device ID is located at absolute address 0x0-0x3. The
ORSO82G5’s device ID is 0xDC012282. More information on the device ID and other Series 4 generic registers
can be found in the MPI/System Bus Application Note.
The ORSO82G5 core registers are clocked by the system bus main clock. If a clock is not provided to the reference
clock, the registers will fail to operate.
The ORSO82G5 core registers do not check for parity on a write operation. On a read operation, no parity is gen-
erated, and a “0” is passed back to the initiating bus master interface on the parity signal line.
Types of Registers
The registers in ORSO82G5 are 8-bit memory locations which, in general, can be classied into several types:
General Core Status Registers
Read-only registers to convey the status information of various operations within the FPSC core. An example is the
state of the LKI-xx receive PLL lock indicator outside the SERDES.
Alarm Status and Mask Registers
The alarm status registers are enabled or masked by the corresponding alarm enable registers. An example of
such an alarm is the Out-Of-Frame (OOF) bit OOF_xx which is enabled by the corresponding alarm enable bit
OOF_ENxx (xx indicates one of the 8 channels AA-BD). (The OOF and BIP error alarms are also available as sig-
nals across the core-FPGA boundary for each channel.) All the alarms for a given channel will be read into a single
status bit (ALARM_STATUS_[AA-BD]). In addition, an event on any of these alarm status bits will generate an inter-
rupt to the FPSC slave of the interrupt cause register on the system bus interface (see technical note TN1017). All
alarm and status registers are clear on read.
Control Registers
Read-write registers to setup the control inputs that dene the operation of the FPSC core. The SERDES block
within the ORSO82G5 core has a set of status and control registers for it’s operation. There is another group of sta-
tus and control registers which are implemented outside the SERDES, which are related to the SERDES and other
functional blocks in the FPSC core. They will be described in detail here.
Each SERDES has four independent channels, which are named A, B, C or D. Using this nomenclature, the SER-
DES A channels are named as AA, AB, AC and AD, while SERDES B channels will be BA, BB,BC and BD. The
register address allocation for the ORSO82G5 is shown in Table 13.. Detailed descriptions of all of the register bits
are provided in Table 14. through Table 22..
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