參數(shù)資料
型號(hào): M-ORSO82G51BM680-DB
廠(chǎng)商: LATTICE SEMICONDUCTOR CORP
元件分類(lèi): FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝: PLASTIC, FBGA-680
文件頁(yè)數(shù): 30/123頁(yè)
文件大小: 2207K
代理商: M-ORSO82G51BM680-DB
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
14
Embedded Core Functional Blocks - Overview
Each channel contains transmit path and receive path logic as shown in Figure 3 and Figure 4. Data are processed
on a channel by channel basis in the SERDES only and SONET modes. Channel by channel processing is also
performed in the Cell mode except in the Input Port Controller (IPC) and Output Port Controller (OPC) blocks. Sup-
port for loopback is also provided but is not shown in Figure 3. The following sections will give an overview of the
pseudo SONET protocol supported by the ORSO82G5 and a top level overview of the macrocells, which provide
the SERDES Only, SONET and Cell Mode functionality.
Figure 3. Top Level Overview, TX Path Logic, Single Channel
FPGA
Logic
Embedded Core
32:8
MUX
Payload
Block
TX
FIFO
OPC2/
OPC8
TOH
Block
SONET
Scrambler
FPGA Data
Cell Processing
SONET Processing
1.0-2.7Gbps
SERDES
8
LDIN
xck311
1:8
dem
ux
8b
REFCLK
(155.52MHZ)
Same pin as
receiver
LEGEND:
TCK39x
TCK78x
TCK156x
TSYSCLKx[A:D]
SYSCLK156x[1,2]
x = A for Quad A, B for Quad B
Divide
by 2
Divide
by 4
Divide
by 2
311 MHz from other
3 links in Quad
77.76MHz
SYSCLK156 8
TSYSCLKx[A:D]
TCK39x
TCK156x
TCK78X
SYSCLK156x[1,2]
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