參數(shù)資料
型號： M-ORSO82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 54/123頁
文件大小： 2207K
代理商： M-ORSO82G51BM680-DB
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
36
Figure 21. Framer State Machine
The framer FSM comes out of reset in the “OOF” state with the OOF alarm set. The framer goes in frame if it nds
2 consecutive frames with the desired framing bytes and goes out of frame if it nds 4 consecutive frames with at
least one framing bit error in each frame. Frame timing is also synchronized based on the STS-48 row and column
counters. This corresponds to SONET specication that it will take two consecutive valid framing patterns to frame
to an incoming signal. Outside the “OOF” state, the OOF alarm output is low.
Section (B1) BIP-8 Calculator
The section BIP-8 B1 byte in a given STS-N frame contains the scrambled BIP value for all scrambled bytes of the
previous frame. Except for the A1,A2 and J0 section overhead bytes, all bytes in a frame are scrambled. The Sec-
tion (B1) BIP-8 is calculated as the even parity of all bits in the current STS-48 frame. This value is compared to the
Section Overhead B1 byte of the next frame. A B1 parity error ag is also generated as a software alarm bit.
Descrambler
The data from the framer is descrambled using the SONET/SDH standard generator polynomial 1 + x
6 + x7. The
descrambling is performed in parallel on each 32-bit word per channel, synchronized to the frame pulse and can be
disabled through the software register bit.
RDI (Remote Defect Indicator) Monitor
The line RDI (RDI-L) is monitored through bits 2-0 of the K2 byte. Within the 32-bit descrambled data, a pattern of
“110” on bits 26-24 will indicate a RDI-L status. RDI-L must be detected in two consecutive frames before an rdi
alarm register bit is set. If fast_frame_mode is enabled, then the RDI alarm register bit will be set if RDI-L is
detected in one frame.
Receive FIFO
Clock domain transfers and multi-link de-skew are one of the most critical parts of this device. The main clock
domain transfer for the datapath is handled by the receive FIFO. For each link, there are two FIFOs. A 24 x 33 FIFO
is used in SONET mode.
The use of the FIFO is controlled by conguration bits.
Data can be sent from the descrambler directly to the FPGA bypassing the alignment FIFO. Data from each
pat_srch
reset
OOF=1
patdet & !ffm
new_frm
in_frm
patdet
OOF=0
!patdet
oof_one
oof_two
oof_three
Legend:
ffm ~ In fast frame mode
AND ffm
!ffm AND
patdet
!patdet
patdet
!patdet
patdet
!patdet
!ffm ~ In regular frame
mode
patdet ~ Correct 4A1/4A2
framing pattern
detected
!patdet ~ Correct 4A1/4A2
framing pattern
NOT detected
!patdet
patdet
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