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| 型號(hào)： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 44/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
27
The received data streams are processed and passed to the FPGA logic as 32-bit words. In SONET mode,
DOUTxx[31:0] carries the 32 bit data from the alignment FIFO of the respective channel and an accompanying
frame pulse, DOUTxx_FP. Other core/FPGA carries miscellaneous information such as OOF, BIPERR, and SPE
indicator. (See Table 10 for details of the core/FPGA receive direction signal assignments.)
Basic SONET Frame Format
An STS-N frame can be broadly divided into the Transport OverHead (TOH) and the Synchronous Payload Enve-
lope (SPE) areas. The TOH comprises of bytes that are used for framing, error detection and various other func-
tions. The start of the SPE can begin at any point in a SONET frame. The start of the SPE is determined using the
pointer bytes located in the TOH. The basic STS-1 frame is shown in Figure 14. Higher rate STS_N signals are
created by byte interleaving N STS-1 signals. Some TOH bytes have slightly different functions in STS-N frames
than in the basic STS-1 frame. The ORSO82G5 offers two options for processing the TOH bytes, as discussed in a
later section.
Figure 14. STS-1 Frame Format
Transport
OverHead
(TOH)
Synchronous Payload Envelope
(SPE)
3 columns
90 Columns
9 Rows
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| M-ORSO82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G51BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
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