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| 型號： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 38/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
21
Detailed Description - SERDES Only Mode
The SERDES only (or bypass) mode is the simplest of the three operating modes for the ORSO82G5. In this
mode, all of the SONET and cell logic block functions are bypassed and data are transferred directly between the
MUX and DEMUX blocks to and from the FPGA interface. This mode is utilized when the user wants to perform all
data processing and uses only the SERDES portion of the Embedded Core. For example, this mode could be uti-
lized to replace an existing design using stand-alone SERDES and FPGAs.
The basic data paths in the transmit and receive directions are shown in Figure 7. In general, the descriptions in
this section are written to describe the SERDES only mode, although the "SERDES blocks" are also used in
SONET and cell mode operation. At the backplane interface, data are transmitted and received serially over eight
pairs of differential 1.0 to 2.7 Gbit/s links. At the FPGA/Embedded Core interface, the data are transferred across
eight 32-bit buses. The SERDES blocks themselves are organized as two blocks (or quads), each supporting four
series links. Each of the eight data paths is identied with a quad and channel identier (i.e., AA,...,BD).
Each channel has a 32-bit TX bus, 32-bit RX bus, a recovered clock, and a transmit clock input.
Figure 7. Basic Data Flows - SERDES Only Mode
Figure 8 shows a block diagram of a single channel of the SERDES block. The transmitter section accepts either
scrambled or un-scrambled data at the parallel input port. It also accepts the low-speed reference clock at the REF-
CLK input and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data are avail-
able at the differential CML output terminated in 86 to drive either an optical transmitter, coaxial media or a circuit
board/backplane.
Cell
Processing
Receive (RX) Path
Transmit (TX) Path
Pseudo-
SONET
Processing
MUX/DEMUX
&
SERDES
ORCA 4E04
FPGA
Logic
Configurable
as
8
data
channels
Organized
in
two
four
channel
blocks
(quads)
User
Configurab
le
I/O
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