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參數(shù)資料
| 型號： | LXT974 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet 10/100 Quad Transceivers |
| 中文描述： | 四10/100快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 68/74頁 |
| 文件大?。?/td> | 1089K |
| 代理商： | LXT974 |
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LXT974/LXT975
—
Fast Ethernet 10/100 Quad Transceivers
68
Datasheet
5.10
Pause
1 = Pause operation is enabled for link partner.
0 = Pause operation is disabled.
RO
N/A
5.9
100BASE-T4
1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.
RO
N/A
5.8
100BASE-TX
full-duplex
1 = Link Partner is 100BASE-TX full-duplex capable.
0 = Link Partner is not 100BASE-TX full-duplex capable.
RO
N/A
5.7
100BASE-TX
1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.
RO
N/A
5.6
10BASE-T
full-duplex
1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex capable.
RO
N/A
5.5
10BASE-T
1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.
RO
N/A
5.4:0
Selector Field
S<4:0>
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negotiation development.
Unspecified or reserved combinations shall not be transmitted.
RO
N/A
Table 50. Auto Negotiation Expansion (Address 6)
Bit
Name
Description
Type
1
Default
6.15:5
Reserved
Ignore on read.
RO
0
6.4
Parallel
Detection Fault
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
RO/
LH
0
6.3
Link Partner
Next Page Able
1 = Link partner is next page able.
0 = Link partner is not next page able.
RO
0
6.2
Next Page Able
Not supported.
RO
0
6.1
Page Received
1 = Three identical and consecutive link code words have been received
from link partner.
0 = Three identical and consecutive link code words have not been
received from link partner.
RO
LH
0
6.0
Link Partner A/
N Able
1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
Table 51. LED Configuration Register (Address 16, Hex 10)
Bit
Name
Description
Type
1
Default
16.15:12
User Defined
No effect on chip operation.
R/W
N/A
16.11:9
Reserved
Ignore on read.
RO
N/A
16.8
TX Pulse Tuning
1 = Faster rise time - May be used to adjust output pulse to match
magnetic performance.
0 = Normal Operation - Provides best match for most magnetics.
R/W
0
1. R/W = Read /Write
Table 49. Auto Negotiation Link Partner Ability Register (Address 5) (Continued)
Bit
Name
Description
Type
1
Default
1. RO = Read Only
相關PDF資料 |
PDF描述 |
|---|---|
| LXT974A | Fast Ethernet 10/100 Quad Transceivers |
| LXT974AHC | Fast Ethernet 10/100 Quad Transceivers |
| LXT974B | Fast Ethernet 10/100 Quad Transceivers |
| LXT974BHC | Fast Ethernet 10/100 Quad Transceivers |
| LXT975 | Fast Ethernet 10/100 Quad Transceivers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LXT974A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974AHC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974B | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974BHC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974QC | 制造商:LEVELONE 功能描述: |
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