參數(shù)資料
型號： LXT974
廠商： Intel Corp.
英文描述： Fast Ethernet 10/100 Quad Transceivers
中文描述： 四10/100快速以太網(wǎng)收發(fā)器
文件頁數(shù)： 15/74頁
文件大?。?/td> 1089K
代理商： LXT974
Fast Ethernet 10/100 Quad Transceivers
—
LXT974/LXT975
Datasheet
15
27
46
65
83
RX_DV0
RX_DV1
RX_DV2
RX_DV3
O
Receive Data Valid - Ports 0 - 3
. These signals are synchronous to the respective
RX_CLK
n
. Active High indication that received code group maps to valid data.
29
48
67
85
RX_ER0
RX_ER1
RX_ER2
RX_ER3
O
Receive Error - Ports 0 - 3
. These signals are synchronous to the respective RX_CLK
n
.
Active High indicates that received code group is invalid, or that PLL is not locked.
28
47
66
84
RX_CLK0
RX_CLK1
RX_CLK2
RX_CLK3
O
Receive Clock - Ports 0 - 3
. 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.
37
57
75
93
COL0
COL1
COL2
COL3
O
Collision Detected - Ports 0 - 3
. Active High outputs asserted upon detection of a collision.
Remain High for the duration of the collision. These signals are generated asynchronously.
Inactive during full-duplex operation.
38
58
76
94
CRS0
CRS1
CRS2
CRS3
O
Carrier Sense - Ports 0 - 3
. Active High signals. During half-duplex operation
(bit 0.8 = 0), CRS
n
is asserted when either transmit or receive medium is non-idle. During
full-duplex operation (bit 0.8 = 1), CRS
n
is asserted only when the receive medium is non-
idle.
MII Control Interface Pins
97
MDIO
I/O
Management Data Input/Output
. Bidirectional serial data channel for PHY/STA
communication.
98
MDINT
OD
Management Data Interrupt
. An active Low output on this pin indicates status change.
Interrupt is cleared by sequentially reading Register 1, then Register 18.
99
MDC
I
Management Data Clock
. Clock for the MDIO serial data channel.
Maximum frequency is 2.5 MHz.
100
MDDIS
I
Management Disable
.
When MDDIS is High, the MDIO is restricted to Read Only and the Hardware Control
Interface pins provide continual control of their respective bits.
When MDDIS is Low at power up or Reset, the Hardware Control Interface pins control only
the initial or
“
default
”
values of their respective register bits. After the power-up/reset cycle is
complete, bit control reverts to the MDIO serial channel.
106
105
104
103
TRSTE0
TRSTE1
TRSTE2
TRSTE3
I
Tristate - Ports 0 - 3
. This bit controls bit 0.10 (Isolate bit). When TRSTE
n
is High, the
respective port isolates itself from the MII Data Interface.
When MDDIS is High, TRSTE provides continuous control over bit 0.10.
When MDDIS is Low, TRSTE sets the initial (default) value of bit 0.10 at Reset and then bit
control reverts back to the MDIO interface.
Table 7. LXT974 and LXT975 MII Signal Descriptions (Continued)
Pin#
3
Symbol
Type
1
Signal Description
2
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an
“
X.Y
”
notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
3. Unused pins should be tied Low.
相關(guān)PDF資料
PDF描述
LXT974A Fast Ethernet 10/100 Quad Transceivers
LXT974AHC Fast Ethernet 10/100 Quad Transceivers
LXT974B Fast Ethernet 10/100 Quad Transceivers
LXT974BHC Fast Ethernet 10/100 Quad Transceivers
LXT975 Fast Ethernet 10/100 Quad Transceivers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT974A 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974AHC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974B 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974BHC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974QC 制造商:LEVELONE 功能描述:
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