參數(shù)資料
型號(hào)： LXT974
廠商： Intel Corp.
英文描述： Fast Ethernet 10/100 Quad Transceivers
中文描述： 四10/100快速以太網(wǎng)收發(fā)器
文件頁(yè)數(shù)： 27/74頁(yè)
文件大?。?/td> 1089K
代理商： LXT974
Fast Ethernet 10/100 Quad Transceivers
—
LXT974/LXT975
Datasheet
27
2.3
Initialization
At power-up or reset, the LXT974/975 performs the initialization as shown in
Figure 11
. Control
mode selection is provided via the MDDIS pin as shown in
Table 18
. When MDDIS (pin 100) is
High, the LXT974/975 operates in Manual Control Mode. When MDDIS is Low, the LXT974/975
operates in MDIO Control Mode.
2.3.1
MDIO Control Mode
In the MDIO Control Mode, the LXT974/975 uses the Hardware Control Interface to set up initial
(default) values of the MDIO registers. The MDIO Register set for the LXT974/975 is described in
Table 44
through
Table 55
. Specific bits in the registers are referenced using an
“
X.Y
”
notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). Once initial values
are set, bit control reverts to the MDIO interface.
2.3.2
Manual Control Mode
In the Manual Control Mode, LXT974/975 disables direct write operations to the MDIO registers
via the MDIO interface. The Hardware Control Interface is continuously monitored and the MDIO
registers are updated accordingly.
Table 17. Configuring the LXT974/975 with Auto-Negotiation Disabled
Desired Configuration
1,2
Pin Settings
MDIO Registers
SD/TP
n
per port
CFG_2
global
CFG_0
global
FDE
global
FDE_FX
0.8
0.13
19.2
Per Port (Fiber) Configuration
Fiber operation can be forced
per port
via SD/TP
n
pins when auto-negotiation is enabled. Per-port settings override the global
pin settings.
100FX Full-Duplex
Operation.
High or
PECL
3
Ignored
Ignored
Ignored
High
1
1
1
100FX Half-Duplex
Operation.
High or
PECL
3
Ignored
Ignored
Ignored
Low
0
1
1
Global (Twisted-Pair) Configuration
5
Force 100TX Full-Duplex
Operation on all ports.
Low
Low
High
High
Ignored
1
1
0
Force 100TX Half-Duplex
Operation on all ports.
Low
Low
High
Low
Ignored
0
1
0
Force 10T Full-Duplex
Operation on all ports.
Low
Low
Low
High
Ignored
1
0
0
Force 10T Half-Duplex
Operation on all ports.
Low
Low
Low
Low
Ignored
0
0
0
1. Refer to
Table 15
for basic configurations.
2. Refer to
Table 16
for Hardware Control Interface functions advertised when auto-negotiation is enabled.
3. When SD/TP
n
is set High or to PECL levels, auto-negotiation is disabled and FDE_FX determines the duplex mode of the
port.
4. CFG_2, CFG_0, and SD/TP
n
must all be set for 100TX operation.
5. Fiber configuration must be selected on a per-port basis.
相關(guān)PDF資料
PDF描述
LXT974A Fast Ethernet 10/100 Quad Transceivers
LXT974AHC Fast Ethernet 10/100 Quad Transceivers
LXT974B Fast Ethernet 10/100 Quad Transceivers
LXT974BHC Fast Ethernet 10/100 Quad Transceivers
LXT975 Fast Ethernet 10/100 Quad Transceivers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT974A 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974AHC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974B 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974BHC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers
LXT974QC 制造商:LEVELONE 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*