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參數(shù)資料
| 型號(hào)： | LXT974 |
| 廠商： | Intel Corp. |
| 英文描述： | Fast Ethernet 10/100 Quad Transceivers |
| 中文描述： | 四10/100快速以太網(wǎng)收發(fā)器 |
| 文件頁(yè)數(shù)： | 22/74頁(yè) |
| 文件大?。?/td> | 1089K |
| 代理商： | LXT974 |
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LXT974/LXT975
—
Fast Ethernet 10/100 Quad Transceivers
22
Datasheet
Transmit Clock
The LXT974/975 is the master clock source for data transmission. The LXT974/975 automatically
sets the speed of TX_CLK to match port conditions. If the port is operating at 100 Mbps, TX_CLK
is set to 25 MHz. If the port is operating at 10 Mbps, TX_CLK is set to 2.5 MHz. The transmit data
and control signals must always be synchronized to TX_CLK by the MAC. The LXT974/975
normally samples these signals on the rising edge of TX_CLK.
However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode,
the LXT974/975 samples the transmit data and control signals on the falling edge of TX_CLK.
When operating under MDIO Control, the user can advance the transmit clock relative to
TXD<3:0> and TX_ER. When Advance TX_CLK Mode is selected, the LXT974/975 clocks TXD
data in on the falling edge of TX_CLK, instead of the rising edge. This mode provides an increase
in timing margins of TXD, relative to TX_CLK. Advance TX_CLK Mode is enabled when bit 19.5
= 1.
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT974/975 asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
For 100TX and 100FX links, RX_DV is asserted from the first nibble of preamble to the last
nibble of the data packet.
For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of
the Start of Frame Delimiter (SFD)
“
5D
”
and remains asserted until the end of the packet.
Error Signals
Whenever the LXT974/975 receives an errored symbol from the network, it asserts RX_ER and
drives
“
1110
”
on the RXD pins.
When the MAC asserts TX_ER, the LXT974/975 drives
“
H
”
symbols out on the line.
Figure 6. MII Data Interface
LXT974/975
Media Access
Controller
MAC
RX_CLK
n
RX_DV
n
RXD<3:0>
n
RX_ER
n
TX_CLK
n
TX_EN
n
TXD<3:0>
n
TX_ER
n
CRS
n
COL
n
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT974A | Fast Ethernet 10/100 Quad Transceivers |
| LXT974AHC | Fast Ethernet 10/100 Quad Transceivers |
| LXT974B | Fast Ethernet 10/100 Quad Transceivers |
| LXT974BHC | Fast Ethernet 10/100 Quad Transceivers |
| LXT975 | Fast Ethernet 10/100 Quad Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT974A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974AHC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974B | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974BHC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
| LXT974QC | 制造商:LEVELONE 功能描述: |
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