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參數(shù)資料
| 型號： | LXT971ALE |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡收發(fā)器|單|的CMOS | QFP封裝| 64管腳|塑料 |
| 文件頁數(shù)： | 66/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT971ALE |
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LXT9784
—
Low-Power Octal PHY
66
Datasheet
Table 54. Reg 20 (14 Hex) 100BASETx Receive Disconnect Counter
Bit(s)
Name
Description
Type
1
20[15:0]
Disconnect
Event
A 16 bit counter that increments for each disconnect event. The counter stops when
full (and does not roll over). Self clears on read.
Two or more consecutive False carrier events causes this counter to increment.
RO
SC
1. RO = Read Only; SC = Self Cleared.
Table 55. Reg 21 (15 Hex) 100BASETx Receive Error Frame Counter
Bit(s)
Name
Description
Type
1
21[15:0]
Receive Error
Frame
A 16 bit counter that increments once per frame for any receive error condition, such
as a symbol error or premature end of frame, in that frame. The counter stops when
full (and does not roll over). Self clears on read.
RO
SC
1. RO = Read Only; SC = Self Cleared.
Table 56. Reg 22 (16 Hex) Receive Symbol Error Counter
Bit(s)
Name
Description
Type
1
22[15:0]
Symbol Error
Counter
A 16-bit counter that increments for each symbol error. The counter stops when full
(and does not roll over). Self clears on read.
RO
SC
1. RO = Read Only; SC = Self Cleared.
Table 57. Reg 23 (17 Hex) 100BASETx Receive Premature End of Frame Error Counter
Bit(s)
Name
Description
Type
1
23[15:0]
Premature End
of Frame
A 16-bit counter that increments for each premature end of frame event. The counter
stops when full (and does not roll over). Self clears on read.
A frame without a
“
TR
”
at the end is considered a premature end of frame event.
RO
SC
1. RO = Read Only; SC = Self Cleared.
Table 58. Reg 24 (18 Hex) 10BASET Receive End of Frame Error Counter
Bit(s)
Name
Description
Type
1
24[15:0]
End of Frame
Counter
A 16-bit counter which increments for each end of frame error event. The counter
stops when full (and does not roll over). Self clears on read.
RO
SC
1. RO = Read Only; SC = Self Cleared.
Table 59. Reg 25 (19 Hex) 10BASET Transmit Jabber Detect Counter
Bit(s)
Name
Description
Type
1
25[15:0]
Jabber detect
counter
A 16-bit counter which increments for each jabber detection event. The counter stops
when full (and does not roll over). Self clears on read.
RO
SC
1. RO = Read Only; SC = Self Cleared.
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