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參數(shù)資料
| 型號： | LXT971ALE |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡收發(fā)器|單|的CMOS | QFP封裝| 64管腳|塑料 |
| 文件頁數(shù)： | 44/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT971ALE |
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LXT9784
—
Low-Power Octal PHY
44
Datasheet
2.12
Test Port Operation
The LXT9784 can be set to one of two manufacturing testing modes, depending on TI, TEXEC,
and TCK input pins combination, as shown in Table 20.
The MODE[2:0] pins are used to enable the manufacturing testing modes, and should be set to
"111".
The test mode can be used only for manufacturing testing.
2.12.1
NAND-Tree Test
This command connects all the outputs of the input-buffers in the device periphery into a NAND-
Tree scheme. All the I/O and outputs, except for MODE[2:0], TI, TEXEC, TCK, INT, and TOUT
pins, are put into a Tri-State mode.
Table 20. Glossary of Protocol Terms
Term
Definition
Preamble
Sequence of 32 contiguous logic one bits on the MDIO pin at the beginning of each transaction
with corresponding cycles on the MDC clock pin for synchronization of the PHY.
Start
A start of Frame pattern of
“
01
”
Opcode
An Operation Code which can assume one of two values:
10 Read instruction.
01 Write instruction.
PHY Adr
5-bit address of the PHY device with MSB transmitted first, which provides support for 32 unique
PHY addresses.
Reg Adr
5-bit address of the specific register within the PHY device with MSB transmitted first. This
provides support for 32 unique registers.
Turnaround
A two-bit turnaround time during which no device actively drives the MDIO signal on a read
cycle. During a read transaction the PHY should not drive MDIO in the first bit time and the drive
a zero in the second bit time. During a write transaction a "10" pattern is driven to PHY.
Data
16 bits of data driven by the PHY on read transaction, and will be driven to PHY on write
transaction. In either case, the MSB is transmitted first.
Idle
The IDLE condition on MDIO is a high impedance state. The MDIO driver is disabled and the
PHY should pull-up the MDIO line to logic one.
Table 21. Test Mode Configuration
Mode Select Pins
1
Test Enable Pins
Mode
Comments
2
1
0
TCK
TI
TEXEC
0
0
1
X
X
X
RMII
Normal System Mode
0
1
0
X
X
X
SMII
1
1
1
0
0
1
NAND Tree (+ Hi Z)
Manufacturing test mode
1
1
1
0
1
0
XNOR Tree (+ Hi Z)
1. Note: All other combinations are
“
reserved
”
and should not be used.
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